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1. general description the gtl2008/GTL2107 is a customized translator between dual xeon processors, platform health management, south bridge and power supply lvttl and gtl signals. functionally and footprint identical to the gtl2007, the gtl2008/GTL2107 lvttl and gtl outputs were changed to put them into a high-impedance state when en1 and en2 are low, with the exception of 11bo because its normal state is low, so it is forced low. en1 and en2 will remain low until v cc is at normal voltage, the other inputs are in valid states and vref is at its proper voltage to assure that the outputs will remain high-impedance through power-up. both the gtl2008/GTL2107 and the gtl2007 are derived from the gtl2006. they add an enable function that disables the error output to the monitoring agent for platforms that monitor the individual error conditions from each processor. this enable function can be used so that false error conditions are not passed to the monitoring agent when the system is unexpectedly powered down. this unexpected power-down could be from a power supply overload, a cpu thermal trip, or some other event of which the monitoring agent is unaware. a typical implementation would be to connect each enable line to the system power good signal or the individual enables to the vrd power good for each processor. typically xeon processors specify a v tt of 1.1 v to 1.2 v, as well as a nominal v ref of 0.73 v to 0.76 v. to allow for future voltage level changes that may extend v ref to 0.63 of v tt (minimum of 0.693 v with v tt of 1.1 v) the gtl2008/GTL2107 allows a minimum v ref of 0.66 v. characterization results show that there is little dc or ac performance variation between these levels. the gtl2008 is the companion chip to the gtl2009 3-bit gtl front-side bus frequency comparator that is used in dual-processor xeon applications. the GTL2107 is the intel designation for the gtl2008. 2. features n operates as a gtl to lvttl sampling receiver or lvttl to gtl driver n en1 and en2 disable error output n all lvttl and gtl outputs are put in a high-impedance state when en1 and en2 are low n 3.0 v to 3.6 v operation n lvttl i/o not 5 v tolerant gtl2008; GTL2107 12-bit gtl to lvttl translator with power good control and high-impedance lvttl and gtl outputs rev. 02 26 september 2006 product data sheet
gtl2008_GTL2107_2 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 02 26 september 2006 2 of 20 philips semiconductors gtl2008; GTL2107 gtl translator with power good control and high-impedance outputs n series termination on the lvttl outputs of 30 w n esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115, and 1000 v cdm per jesd22-c101 n latch-up testing is done to jedec standard jesd78 class ii, level a which exceeds 500 ma n package offered: tssop28 3. quick reference data 4. ordering information the GTL2107 is the intel designation for the gtl2008 and is identical to the gtl2008 except for the type number and the topside markings. table 1. quick reference data t amb =25 c symbol parameter conditions min typ max unit c io input/output capacitance a port; v o = 3.0 v or 0 v - 2.5 3.5 pf b port; v o =v tt or 0 v - 1.5 2.5 pf v ref = 0.73 v; v tt = 1.1 v t plh low-to-high propagation delay na to nbi; see figure 4 14 8ns nbi to na or nao (open-drain outputs); see figure 14 21318ns t phl high-to-low propagation delay na to nbi; see figure 4 2 5.5 10 ns nbi to na or nao (open-drain outputs); see figure 14 2 4 10 ns v ref = 0.76 v; v tt = 1.2 v t plh low-to-high propagation delay na to nbi; see figure 4 14 8ns nbi to na or nao (open-drain outputs); see figure 14 21318ns t phl high-to-low propagation delay na to nbi; see figure 4 2 5.5 10 ns nbi to na or nao (open-drain outputs); see figure 14 2 4 10 ns table 2. ordering information t amb = - 40 c to +85 c type number topside mark package name description version gtl2008pw gtl2008 tssop28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm sot361-1 GTL2107pw GTL2107 tssop28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm sot361-1
gtl2008_GTL2107_2 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 02 26 september 2006 3 of 20 philips semiconductors gtl2008; GTL2107 gtl translator with power good control and high-impedance outputs 5. functional diagram (1) the enable on 7bo1/7bo2 include a delay that prevents the transient condition where 5bi/6bi go from low to high, and the low to high on 5a/6a lags up to 100 ns from causing a low glitch on the 7bo1/7bo2 outputs. (2) the 11bo output is driven low after v cc is powered up with en2 low to prevent reporting of a fault condition before en2 goes high. fig 1. logic diagram of gtl2008/GTL2107 002aab968 gtl2008/GTL2107 1bi 2bi 27 26 gtl inputs 7bo1 25 7bo2 24 gtl outputs en2 23 lvttl input 11bo 22 gtl output delay (1) 5bi 6bi 21 20 3bi 19 4bi 18 delay (1) gtl inputs 7 11bi 8 11a 9 9bi lvttl input/output (open-drain) gtl input gtl input 1 vref 2 1ao 3 2ao 4 5a 5 6a 6 en1 lvttl input gtl lvttl inputs/outputs (open-drain) lvttl outputs (open-drain) 10 3ao 11 4ao lvttl outputs (open-drain) 10bo1 17 10bo2 16 gtl outputs 12 10ai1 13 10ai2 lvttl inputs 9ao 15 lvttl output (2) 1 1 & & 1
gtl2008_GTL2107_2 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 02 26 september 2006 4 of 20 philips semiconductors gtl2008; GTL2107 gtl translator with power good control and high-impedance outputs 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin con?guration for tssop28 gtl2008pw GTL2107pw vref v cc 1ao 1bi 2ao 2bi 5a 7bo1 6a 7bo2 en1 en2 11bi 11bo 11a 5bi 9bi 6bi 3ao 3bi 4ao 4bi 10ai1 10bo1 10ai2 10bo2 gnd 9ao 002aab969 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 18 17 20 19 22 21 24 23 26 25 28 27 table 3. pin description symbol pin description vref 1 gtl reference voltage 1ao 2 data output (lvttl), open-drain 2ao 3 data output (lvttl), open-drain 5a 4 data input/output (lvttl), open-drain 6a 5 data input/output (lvttl), open-drain en1 6 enable input (lvttl) 11bi 7 data input (gtl) 11a 8 data input/output (lvttl), open-drain 9bi 9 data input (gtl) 3ao 10 data output (lvttl), open-drain 4ao 11 data output (lvttl), open-drain 10ai1 12 data input (lvttl) 10ai2 13 data input (lvttl) gnd 14 ground (0 v) 9ao 15 data output (lvttl), 3-state 10bo2 16 data output (gtl) 10bo1 17 data output (gtl) 4bi 18 data input (gtl) 3bi 19 data input (gtl)
gtl2008_GTL2107_2 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 02 26 september 2006 5 of 20 philips semiconductors gtl2008; GTL2107 gtl translator with power good control and high-impedance outputs 7. functional description refer to figure 1 logic diag r am of gtl2008/GTL2107 . 7.1 function tables [1] 1ao, 2ao, 3ao, 4ao and 5a/6a condition changed by enn power good signal as described in t ab le 5 and t ab le 6 . 6bi 20 data input (gtl) 5bi 21 data input (gtl) 11bo 22 data output (gtl) en2 23 enable input (lvttl) 7bo2 24 data output (gtl) 7bo1 25 data output (gtl) 2bi 26 data input (gtl) 1bi 27 data input (gtl) v cc 28 positive supply voltage table 3. pin description continued symbol pin description table 4. gtl input signals h = high voltage level; l = low voltage level. input output [1] 1bi/2bi/3bi/4bi/9bi 1ao/2ao/3ao/4ao/9ao ll hh table 5. en1 power good signal h = high voltage level; l = low voltage level. en1 1ao and 2ao 5a l 1bi and 2bi disconnected (high-z) 5bi disconnected h follows bi 5bi connected table 6. en2 power good signal h = high voltage level; l = low voltage level. en2 3ao and 4ao 6a l 3bi and 4bi disconnected (high-z) 6bi disconnected h follows bi 6bi connected
gtl2008_GTL2107_2 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 02 26 september 2006 6 of 20 philips semiconductors gtl2008; GTL2107 gtl translator with power good control and high-impedance outputs [1] the enable on 7bo1/7bo2 includes a delay that prevents the transient condition where 5bi/6bi go from low to high, and the low to high on 5a/6a lags up to 100 ns from causing a low glitch on the 7bo1/7bo2 outputs. [2] open-drain input/output terminal is driven to logic low state by other driver. [1] open-drain input/output terminal is driven to logic low state by other driver. table 7. smi signals h = high voltage level; l = low voltage level; x = dont care. inputs output 10ai1/10ai2 en2 9bi 10bo1/10bo2 lhll l hhl hhl l hhhh llxl hl xh table 8. prochot signals h = high voltage level; l = low voltage level. input input/output output 5bi/6bi 5a/6a (open-drain) 7bo1/7bo2 llh [1] hl [2] l hhh table 9. nmi signals h = high voltage level; l = low voltage level; x = dont care. inputs input/output output 11bi en2 11a (open-drain) 11bo l hhl lhl [1] h hhl h xl hl xl l [1] h
gtl2008_GTL2107_2 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 02 26 september 2006 7 of 20 philips semiconductors gtl2008; GTL2107 gtl translator with power good control and high-impedance outputs 8. application design-in information (1) if 9ao needs to be high before en2 goes high, a pull-up resistor is required because it is high-impedance until en2 goes high. all other outputs, both gtl and lvttl, require pull-up resistors because they are open-drain. fig 3. typical application thrmtrip l cpu1 ierr_l forcepr_l cpu2 disable_l gtl2008 GTL2107 prochot l forcepr_l prochot l thrmtrip l ierr_l cpu1 disable_l cpu2 nmi nmi 10bo2 10bo1 4bi 3bi 6bi 5bi en2 7bo2 7bo1 2bi 1bi 1ao 2ao 5a 6a 11a 3ao 4ao 10ai1 10ai2 en1 gnd 9bi 9ao platform health management cpu1 1err_l cpu1 thrmtrip l cpu1 prochot l cpu2 prochot l nmi_l cpu2 ierr_l cpu2 thrmtrip l cpu1 smi l cpu2 smi l smi_buff_l southbridge nmi southbridge smi_l power supply power good 1.5 k w to 1.2 k w v cc v tt 56 w 1.5 k w r 2r vref 11b1 v cc v cc 11b0 002aab970 56 w v tt (1)
gtl2008_GTL2107_2 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 02 26 september 2006 8 of 20 philips semiconductors gtl2008; GTL2107 gtl translator with power good control and high-impedance outputs 9. limiting values [1] the input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] current into any output in the low state. [3] current into any output in the high state. [4] the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create j unction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not excee d 150 c. 10. recommended operating conditions table 10. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (groun d=0v). symbol parameter conditions min max unit v cc supply voltage - 0.5 +4.6 v i ik input clamping current v i <0v - - 50 ma v i input voltage a port (lvttl) - 0.5 [1] +4.6 v b port (gtl) - 0.5 [1] +4.6 v i ok output clamping current v o <0v - - 50 ma v o output voltage output in off or high state; a port - 0.5 [1] +4.6 v output in off or high state; b port - 0.5 [1] +4.6 v i ol low-level output current [2] a port - 32 ma b port - 30 ma i oh high-level output current [3] a port - - 32 ma t stg storage temperature - 60 +150 c t j(max) maximum junction temperature [4] - +125 c table 11. operating conditions symbol parameter conditions min typ max unit v cc supply voltage 3.0 3.3 3.6 v v tt termination voltage gtl - 1.2 - v v ref reference voltage gtl 0.64 0.8 1.1 v v i input voltage a port 0 3.3 3.6 v b port 0 v tt 3.6 v v ih high-level input voltage a port and enn 2 - - v b port v ref + 0.050 - - v v il low-level input voltage a port and enn - - 0.8 v b port - - v ref - 0.050 v i oh high-level output current a port - - - 16 ma i ol low-level output current a port - - 16 ma b port - - 15 ma t amb ambient temperature operating in free-air - 40 - +85 c
gtl2008_GTL2107_2 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 02 26 september 2006 9 of 20 philips semiconductors gtl2008; GTL2107 gtl translator with power good control and high-impedance outputs 11. static characteristics [1] all typical values are measured at v cc = 3.3 v and t amb =25 c. [2] the input and output voltage ratings may be exceeded if the input and output current ratings are observed. [3] this is the increase in supply current for each input that is at the speci?ed lvttl voltage level rather than v cc or gnd. table 12. static characteristics recommended operating conditions; voltages are referenced to gnd (ground = 0 v). t amb = - 40 c to +85 c symbol parameter conditions min typ [1] max unit v oh high-level output voltage 9ao; v cc = 3.0 v to 3.6 v; i oh = - 100 m a [2] v cc - 0.2 3.0 - v 9ao; v cc = 3.0 v; i oh = - 16 ma [2] 2.1 2.3 - v v ol low-level output voltage a port; v cc = 3.0 v; i ol =4ma [2] - 0.15 0.4 v a port; v cc = 3.0 v; i ol =8ma [2] - 0.3 0.55 v a port; v cc = 3.0 v; i ol =16ma [2] - 0.6 0.8 v b port; v cc = 3.0 v; i ol =15ma [2] - 0.13 0.4 v i oh high-level output current open-drain outputs; a port other than 9ao; v o =v cc ; v cc = 3.6 v -- 1 m a i i input current a port; v cc = 3.6 v; v i =v cc -- 1 m a a port; v cc = 3.6 v; v i =0v - - 1 m a b port; v cc = 3.6 v; v i =v tt or gnd - - 1 m a i cc supply current a or b port; v cc = 3.6 v; v i =v cc or gnd; i o =0ma - 8 12 ma d i cc [3] additional supply current per input; a port or control inputs; v cc = 3.6 v; v i =v cc - 0.6 v - - 500 m a c io input/output capacitance a port; v o = 3.0 v or 0 v - 2.5 3.5 pf b port; v o =v tt or 0 v - 1.5 2.5 pf
gtl2008_GTL2107_2 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 02 26 september 2006 10 of 20 philips semiconductors gtl2008; GTL2107 gtl translator with power good control and high-impedance outputs 12. dynamic characteristics table 13. dynamic characteristics v cc = 3.3 v 0.3 v symbol parameter conditions min typ [1] max unit v ref = 0.73 v; v tt = 1.1 v t plh low-to-high propagation delay na to nbi; see figure 4 148ns 9bi to 9ao; see figure 5 2 5.5 10 ns nbi to na or nao (open-drain outputs); see figure 14 21318ns 9bi to 10bon 2 6 11 ns 11a to 11bo; see figure 10 148ns 11bi to 11a; see figure 9 2 7.5 11 ns 11bi to 11bo 2 8 13 ns 5bi to 7bo1 or 6bi to 7bo2; see figure 7 4 7 12 ns t phl high-to-low propagation delay na to nbi; see figure 4 2 5.5 10 ns 9bi to 9ao; see figure 5 2 5.5 10 ns nbi to na or nao (open-drain outputs); see figure 14 2 4 10 ns 9bi to 10bon 2 6 11 ns 11a to 11bo; see figure 10 1 5.5 10 ns 11bi to 11a; see figure 9 2 8.5 13 ns 11bi to 11bo [2] 21421ns 5bi to 7bo1 or 6bi to 7bo2; see figure 7 100 205 350 ns t plz low to off-state propagation delay en1 to nao or en2 to nao; see figure 8 1 3 10 ns en1 to 5a (i/o) or en2 to 6a (i/o); see figure 8 137ns t pzl off-state to low propagation delay en1 to nao or en2 to nao; see figure 8 2 7 10 ns en1 to 5a (i/o) or en2 to 6a (i/o); see figure 8 2 7 10 ns t phz high to off-state propagation delay en2 to 9ao; see figure 11 2 5 10 ns t pzh off-state to high propagation delay en2 to 9ao; see figure 11 1 4 10 ns
gtl2008_GTL2107_2 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 02 26 september 2006 11 of 20 philips semiconductors gtl2008; GTL2107 gtl translator with power good control and high-impedance outputs [1] all typical values are at v cc = 3.3 v and t amb =25 c. [2] includes ~7.6 ns rc rise time of test load pull-up on 11a, 1.5 k w pull-up and 21 pf load on 11a has about 23 ns rc rise time. v ref = 0.76 v; v tt = 1.2 v t plh low-to-high propagation delay na to nbi; see figure 4 148ns 9bi to 9ao; see figure 5 2 5.5 10 ns nbi to na or nao (open-drain outputs); see figure 14 21318ns 9bi to 10bon 2 6 11 ns 11a to 11bo; see figure 10 148ns 11bi to 11a; see figure 9 2 7.5 11 ns 11bi to 11bo 2 8 13 ns 5bi to 7bo1 or 6bi to 7bo2; see figure 7 4 7 12 ns t phl high-to-low propagation delay na to nbi; see figure 4 2 5.5 10 ns 9bi to 9ao; see figure 5 2 5.5 10 ns nbi to na or nao (open-drain outputs); see figure 14 2 4 10 ns 9bi to 10bon 2 6 11 ns 11a to 11bo; see figure 10 1 5.5 10 ns 11bi to 11a; see figure 9 2 8.5 13 ns 11bi to 11bo [2] 21421ns 5bi to 7bo1 or 6bi to 7bo2; see figure 7 100 205 350 ns t plz low to off-state propagation delay en1 to nao or en2 to nao; see figure 8 1 3 10 ns en1 to 5a (i/o) or en2 to 6a (i/o); see figure 8 137ns t pzl off-state to low propagation delay en1 to nao or en2 to nao; see figure 8 2 7 10 ns en1 to 5a (i/o) or en2 to 6a (i/o); see figure 8 2 7 10 ns t phz high to off-state propagation delay en2 to 9ao; see figure 11 2 5 10 ns t pzh off-state to high propagation delay en2 to 9ao; see figure 11 2 4 10 ns table 13. dynamic characteristics continued v cc = 3.3 v 0.3 v symbol parameter conditions min typ [1] max unit
gtl2008_GTL2107_2 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 02 26 september 2006 12 of 20 philips semiconductors gtl2008; GTL2107 gtl translator with power good control and high-impedance outputs 12.1 waveforms v m = 1.5 v at v cc 3 3.0 v for a ports; v m =v ref for b ports. v m = 1.5 v for a port and v ref for b port a port to b port a. pulse duration b. propagation delay times fig 4. voltage waveforms 002aaa999 v oh 0 v t p v m v m 002aab000 3.0 v 0 v v tt v ol t plh t phl v ref v ref 1.5 v 1.5 v input output prr 10 mhz; z o =50 w ; t r 2.5 ns; t f 2.5 ns fig 5. propagation delay, 9bi to 9ao fig 6. nbi to na (i/o) or nbi to nao open-drain outputs fig 7. 5bi to 7bo1 or 6bi to 7bo2 fig 8. en1 to 5a (i/o) or en2 to 6a (i/o) or en1 to nao or en2 to nao 002aab001 v tt 1 / 3 v tt v oh v ol t plh t phl 1.5 v 1.5 v v ref v ref input output 002aab002 v tt 1 / 3 v tt v cc t plz t pzl v ref v ref input output v ol + 0.3 v 1.5 v 002aac195 v tt 1 / 3 v tt v tt v ol t plh t phl v ref v ref input output v ref v ref 002aab005 3.0 v 0 v v oh v ol t plz t pzl 1.5 v 1.5 v input output 1.5 v v ol + 0.3 v
gtl2008_GTL2107_2 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 02 26 september 2006 13 of 20 philips semiconductors gtl2008; GTL2107 gtl translator with power good control and high-impedance outputs fig 9. 11bi to 11a fig 10. 11a to 11bo fig 11. en2 to 9ao 002aac196 v tt 0 v v oh v ol t plz t pzl v ref v ref input output 1.5 v v ol + 0.3 v 002aac197 3.0 v 0 v v tt v ol t plh t phl v ref v ref 1.5 v 1.5 v input output 002aab980 3.0 v 0 v v oh v ol t phz t pzh 1.5 v 1.5 v input output 1.5 v v ol + 0.3 v
gtl2008_GTL2107_2 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 02 26 september 2006 14 of 20 philips semiconductors gtl2008; GTL2107 gtl translator with power good control and high-impedance outputs 13. test information r l load resistor c l load capacitance; includes jig and probe capacitance r t termination resistance; should be equal to z o of pulse generators. fig 12. load circuit for a outputs (9ao) fig 13. load circuit for b outputs fig 14. load circuit for open-drain lvttl i/o and open-drain outputs fig 15. load circuit for 9ao off-state to low and low to off-state pulse generator v o c l 50 pf 002aab981 r l 500 w r t v i v cc dut pulse generator dut v o c l 30 pf 50 w 002aab264 r t v i v cc v tt pulse generator dut v o c l 21 pf r l 1.5 k w 002aab265 r t v i v cc v cc pulse generator dut v o c l 50 pf r l 500 w 002aab982 r t v i v cc 6 v r l 500 w
gtl2008_GTL2107_2 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 02 26 september 2006 15 of 20 philips semiconductors gtl2008; GTL2107 gtl translator with power good control and high-impedance outputs 14. package outline fig 16. package outline sot361-1 (tssop28) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 9.8 9.6 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.8 0.5 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot361-1 mo-153 99-12-27 03-02-19 0.25 w m b p z e 114 28 15 pin 1 index q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a d y 0 2.5 5 mm scale tssop28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm sot361-1 a max. 1.1
gtl2008_GTL2107_2 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 02 26 september 2006 16 of 20 philips semiconductors gtl2008; GTL2107 gtl translator with power good control and high-impedance outputs 15. soldering 15.1 introduction to soldering surface mount packages there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. 15.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. typical re?ow temperatures range from 215 cto260 c depending on solder paste material. the peak top-surface temperature of the packages should be kept below: moisture sensitivity precautions, as indicated on packing, must be respected at all times. 15.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): table 14. snpb eutectic process - package peak re?ow temperatures (from j-std-020c july 2004) package thickness volume mm 3 < 350 volume mm 3 3 350 < 2.5 mm 240 c+0/ - 5 c 225 c+0/ - 5 c 3 2.5 mm 225 c+0/ - 5 c 225 c+0/ - 5 c table 15. pb-free process - package peak re?ow temperatures (from j-std-020c july 2004) package thickness volume mm 3 < 350 volume mm 3 350 to 2000 volume mm 3 > 2000 < 1.6 mm 260 c + 0 c 260 c + 0 c 260 c + 0 c 1.6 mm to 2.5 mm 260 c + 0 c 250 c + 0 c 245 c + 0 c 3 2.5 mm 250 c + 0 c 245 c + 0 c 245 c + 0 c
gtl2008_GTL2107_2 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 02 26 september 2006 17 of 20 philips semiconductors gtl2008; GTL2107 gtl translator with power good control and high-impedance outputs C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 15.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 c and 320 c. 15.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . table 16. suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, vfbga, xson not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5] [6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
gtl2008_GTL2107_2 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 02 26 september 2006 18 of 20 philips semiconductors gtl2008; GTL2107 gtl translator with power good control and high-impedance outputs [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages. 16. abbreviations 17. revision history table 17. abbreviations acronym description cdm charged device model cmos complementary metal oxide semiconductor cpu central processing unit dut device under test esd electrostatic discharge gtl gunning transceiver logic hbm human body model lvttl low voltage transistor-transistor logic mm machine model prr pulse rate repetition ttl transistor-transistor logic vrd voltage regulator down table 18. revision history document id release date data sheet status change notice supersedes gtl2008_GTL2107_2 20060926 product data sheet - gtl2008_1 modi?cations: ? added type number gtl2017 ? section 1 gener al descr iption : added new 7th paragraph ? section 4 order ing inf or mation : added type number GTL2107pw to t ab le 2 order ing inf or mation and following paragraph ? t ab le 10 limiting v alues : removed (old) table note 1 (information is now in section 18 legal inf or mation ) ? added dut to t ab le 17 ab bre viations gtl2008_1 20060502 product data sheet - -
gtl2008_GTL2107_2 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 02 26 september 2006 19 of 20 philips semiconductors gtl2008; GTL2107 gtl translator with power good control and high-impedance outputs 18. legal information 18.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .semiconductors .philips .com. 18.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. philips semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local philips semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 18.3 disclaimers general information in this document is believed to be accurate and reliable. however, philips semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes philips semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use philips semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a philips semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. philips semiconductors accepts no liability for inclusion and/or use of philips semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale philips semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .semiconductors .philips .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by philips semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 18.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 19. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
philips semiconductors gtl2008; GTL2107 gtl translator with power good control and high-impedance outputs ? koninklijke philips electronics n.v. 2006. all rights reserved. for more information, please visit: http://www.semiconductors.philips.com. for sales office addresses, email to: sales.addresses@www.semiconductors.philips.com. date of release: 26 september 2006 document identifier: gtl2008_GTL2107_2 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 5 7.1 function tables . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 application design-in information . . . . . . . . . . 7 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 10 recommended operating conditions. . . . . . . . 8 11 static characteristics. . . . . . . . . . . . . . . . . . . . . 9 12 dynamic characteristics . . . . . . . . . . . . . . . . . 10 12.1 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 test information . . . . . . . . . . . . . . . . . . . . . . . . 14 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 15 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 15.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 15.2 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 16 15.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 16 15.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 17 15.5 package related soldering information . . . . . . 17 16 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 18 legal information. . . . . . . . . . . . . . . . . . . . . . . 19 18.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 18.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 18.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 18.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 contact information. . . . . . . . . . . . . . . . . . . . . 19 20 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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